The related art will be described below with reference to FIG. 12 and FIG. 13.
First, the structure of an example of the related art will be described.
FIG. 12 is a pixel circuit of an organic light emitting diode (OLED) display according to the related art. Each of pixels 213 is provided with an OLED element 201, and one end of the OLED element 201 is connected to a common electrode while the other end is connected to a power supply line 212 via an AZB switch 202 and a drive thin film transistor (drive TFT) 203. An AZ switch 204 is connected between the gate and drain of the drive TFT 203, and a memory capacitor 205 is connected between its gate and source. The gate of the drive TFT 203 is connected to a signal line 211 via an offset-cancellation capacitor 206 and a pixel switch 207. Incidentally, the AZB switch 202 is controlled by an AZB control line 208, the AZ switch 204 by an AZ control line 209, and the pixel switch 207 by a gate line 210.
Next, the operation of this example of the related art will be described with reference to FIG. 13.
FIG. 13 is an operation timing chart of writing signal voltages into pixels according to the related art. Since the AZB switch 202, the AZ switch 204 and the pixel switch 207 are pMOSs as shown in FIG. 12, in the waveforms shown in FIG. 13, the lower level corresponds to the ON state of the respective switches, and the upper level, to the OFF state of the same.
In a pixel selected for writing, at first the pixel switch 207 is turned ON in response to a signal SEL on the gate line 210, and the AZ switch 204 is turned ON by the AZ control line 209. As the AZB switch 202 is ON then, a current flows from the power supply line 212 via the drive TFT 203 diode-connected to the OLED element 201.
Next, when the AZB switch 202 is turned OFF in response to a signal on the AZB control line 208, the drive TFT 203 is turned OFF at the time the drain end of the drive TFT 203 has reached a threshold voltage Vth. Signal voltage data (DAT) of a “0 level” is applied then to the signal line 211, and the difference between this voltage and the threshold voltage Vth is entered into the offset-cancellation capacitor 206.
Next, after the AZ switch 204 is turned OFF in response to a signal on the AZ control line 209, an image signal voltage is applied to the signal line 211. A voltage matching the image signal voltage is generated at the gate of the drive TFT 203 as the threshold voltage Vth, and this voltage is caused by the turning-OFF of the pixel switch 207 in response to the signal SEL on the gate line 210 to be stored into the memory capacitor 205. After that, the turning-ON of the AZB switch 202 completes the writing of the signal voltage into the pixels 213, and the OLED element 201 keeps on emitting light at a level of brightness matching the image signal voltage.
Such an example of the related art is described in Non-Patent Document 1 for instance.
Besides that, techniques of modulating and driving OLED elements by using a triangular waveform are disclosed in Patent Document 1 and Patent Document 2.
Patent Document 1: Japanese Patent Laid-Open No. 2003-005709
Patent Document 2: Japanese Patent Laid-Open No. 2003-122301
Non-Patent Document: 1998 SID Digest of Technical Papers, pp. 11-14